Microarchitectural synthesis of performance-constrained, low-power VLSI designs
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 11 references indexed in Scilit:
- Low-power Signal Processing SystemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- An Approach For Power Minimization Using TransformationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint SatisfactionVLSI Design, 1997
- Transition density: a new measure of activity in digital circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Power dissipation of VLSI array processing systemsJournal of Signal Processing Systems, 1992
- Scheduling for functional pipelining and loop windingPublished by Association for Computing Machinery (ACM) ,1991
- Force-directed scheduling for the behavioral synthesis of ASICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Sehwa: a software package for synthesis of pipelines from behavioral specificationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuitsIEEE Journal of Solid-State Circuits, 1984
- Optimizing Synchronous Circuitry by Retiming (Preliminary Version)Published by Springer Nature ,1983