Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits
- 1 February 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-35 (2) , 157-161
- https://doi.org/10.1109/TC.1986.1676733
Abstract
The use of quaternary logic input and output signals for delivering information on and off chip could reduce the number of required package pins or increase the amount of information conveyed on a fixed number of package pins. In this correspondence, we discuss the performance of prototype CMOS binary-to-quaternary encoder and quaternary-to-binary decoder test circuits that have been realized on a gate array IC chip.Keywords
This publication has 4 references indexed in Scilit:
- A 4-valued ECL encoder and decoder circuitIEEE Journal of Solid-State Circuits, 1982
- Implementing Parallel Counters with Four-Valued Threshold LogicIEEE Transactions on Computers, 1979
- Design considerations in single-channel MOS analog integrated circuits-a tutorialIEEE Journal of Solid-State Circuits, 1978
- Design of Ternary COS/MOS Memory and Sequential CircuitsIEEE Transactions on Computers, 1977