A 4-valued ECL encoder and decoder circuit
- 1 June 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (3) , 547-552
- https://doi.org/10.1109/JSSC.1982.1051773
Abstract
The authors present the prototype of a 4-valued ECL encoder and decoder circuit that has been designed as a test chip for the realization of 4-valued cells to be used in interconnection networks. The hardware implementation of such a network in a SIMD or a MIMD computer architecture leads to a significant reduction of the number of wires. Static and dynamic characteristics are presented together with results on the propagation of 4-valued signals. Noise margins are compared for 2-valued and 4-valued versions.Keywords
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