CMOS squarer and four-quadrant multiplier
- 1 January 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 42 (2) , 119-122
- https://doi.org/10.1109/81.372853
Abstract
A CMOS squarer and a four-quadrant multiplier using the MOS transistors operated in saturation are presented. Simulation results are given to verify the theoretical analysis. The multiplier has a nonlinearity error less than 1% over ±2 V input range and a -3 dB bandwidth of 5 MHz. The total harmonic distortion is less than 2.5% with input range up to ±2 V. The squarer has a nonlinearity error less than 1% over ±1.95 V input range. The second-order effect caused by the mobility reduction is discussed. The proposed circuits will be useful in analog signal-processing applicationsKeywords
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