Dynamic precision management for loop computations on reconfigurable architectures
- 20 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 249-258
- https://doi.org/10.1109/fpga.1999.803687
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- The design and implementation of a context switching FPGAPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A variable long-precision arithmetic unit design for reconfigurable coprocessor architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Object oriented circuit-generators in JavaPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- PAM-Blox: high performance FPGA design for adaptive computingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Garp: a MIPS processor with a reconfigurable coprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A time-multiplexed FPGAPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- String matching on multicontext FPGAs using self-reconfigurationPublished by Association for Computing Machinery (ACM) ,1999
- Programmable active memories: reconfigurable systems come of ageIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1996
- Implementation of a 2-D fast Fourier transform on an FPGA-based custom computing machinePublished by Springer Nature ,1995
- Using reconfigurable hardware to speed up product development and performancePublished by Springer Nature ,1995