High level synthesis for reconfigurable datapath structures
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
High level synthesis techniques for the synthesis of restructurable datapaths are introduced. The techniques can be used in applications such as design for fault tolerance against permanent faults, design for yield improvement, and design of application specific programmable processors. The paper focuses on design techniques for built in self repair (BISR), which addresses the first two of these applications. The new BISR methodology consists of two approaches which exploit the design space exploration abilities of high level synthesis. The first method uses resource allocation, assignment, and scheduling, and the second uses transformations. The effectiveness of the approaches are verified on a set of benchmark examples.Keywords
This publication has 6 references indexed in Scilit:
- Transformation-based high-level synthesis of fault-tolerant ASICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A new statistical approach for fault-tolerant VLSI systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- High level synthesis for reconfigurable datapath structuresPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fast prototyping of datapath-intensive architecturesIEEE Design & Test of Computers, 1991
- Automated micro-roll-back self-recovery synthesisPublished by Association for Computing Machinery (ACM) ,1991
- The high-level synthesis of digital systemsProceedings of the IEEE, 1990