A new statistical approach for fault-tolerant VLSI systems
- 2 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A novel approach to the statistics of fault-tolerant VLSI systems is presented by compounding binomial distributions with a beta distribution. This technique was discovered in the analysis of fault-tolerant dynamic random-access memory (DRAM) chips. Manufacturing data supporting this method are shown and the application of the approach to standard fault-tolerance schemes is described. Special forms of these statistics for computer calculations are also discussed and examples are given.Keywords
This publication has 18 references indexed in Scilit:
- Improved yield models for fault-tolerant random-access memory chipsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A unified negative-binomial distribution for yield analysis of defect-tolerant circuitsIEEE Transactions on Computers, 1993
- The evaluation of 16-Mbit memory chips with built-in reliabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyondIEEE Journal of Solid-State Circuits, 1991
- A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECCIEEE Journal of Solid-State Circuits, 1990
- Block Alignment: A Method for Increasing the Yield of Memory Chips That are Partially GoodPublished by Springer Nature ,1989
- Defect and Fault Tolerance in VLSI SystemsPublished by Springer Nature ,1989
- Modeling the Effect of Redundancy on Yield and Performance of VLSI SystemsIEEE Transactions on Computers, 1987
- On Area and Yield Considerations for Fault-Tolerant VLSI Processor ArraysIEEE Transactions on Computers, 1984
- Defect density distribution for LSI yield calculationsIEEE Transactions on Electron Devices, 1973