Dynamic flip-flop with improved power
- 1 January 2000
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 323-326
- https://doi.org/10.1109/iccd.2000.878303
Abstract
An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while preserving logic embedding property. This is accomplished by equalizing the tpLHand tpHLof the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.Keywords
This publication has 3 references indexed in Scilit:
- Flow-through latch and edge-triggered flip-flop hybrid elementsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Semi-dynamic and dynamic flip-flops with embedded logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systemsIEEE Journal of Solid-State Circuits, 1999