Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
- 1 April 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 34 (4) , 536-548
- https://doi.org/10.1109/4.753687
Abstract
In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high- performance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bot- tlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip- flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.Keywords
This publication has 12 references indexed in Scilit:
- CMOS circuit speed optimization based on switch level simulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Flow-through latch and edge-triggered flip-flop hybrid elementsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Semi-dynamic and dynamic flip-flops with embedded logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings"IEEE Journal of Solid-State Circuits, 1997
- New single-clock CMOS latches and flipflops with improved speed and power savingsIEEE Journal of Solid-State Circuits, 1997
- Circuit techniques in a 266-MHz MMX-enabled processorIEEE Journal of Solid-State Circuits, 1997
- A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessorIEEE Journal of Solid-State Circuits, 1996
- A 2.2 W, 80 MHz superscalar RISC microprocessorIEEE Journal of Solid-State Circuits, 1994
- A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop schemeIEEE Journal of Solid-State Circuits, 1994
- Theory of CMOS Digital Circuits and Circuit FailuresPublished by Walter de Gruyter GmbH ,1992