Median filter architecture based on sorting networks
- 2 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 3, 1069-1072
- https://doi.org/10.1109/iscas.1992.230295
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- VLSI Architecture for a one chip video median filterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- High sample rate systolic architectures for median filtersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Systolic architecture for 2-D rank order filteringPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Architectures and design techniques for real-time image-processing IC'sIEEE Journal of Solid-State Circuits, 1987
- Design and implementation of a single-chip 1-D median filterIEEE Transactions on Acoustics, Speech, and Signal Processing, 1983
- Getting the Median FasterComputer Graphics and Image Processing, 1981
- Systolic Algorithms for Running Order Statistics in Signal and Image ProcessingPublished by Springer Nature ,1981