Design procedure for two-stage CMOS operational amplifiers employing current buffer
- 14 November 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
- Vol. 52 (11) , 766-770
- https://doi.org/10.1109/tcsii.2005.852530
Abstract
The design procedure of the two-stage CMOS operational amplifiers employing Miller capacitor in conjunction with the common-gate current buffer is presented. Unlike the previously reported design strategy of the opamp of this type, which results in the opamp with a pair of nondominant complex conjugate poles and a finite zero, the proposed procedure is based upon the design strategy that results in the opamp with only one dominant pole. Design example of the proposed procedure is given.Keywords
This publication has 4 references indexed in Scilit:
- Design procedure for two-stage CMOS opamp with flexible noise-power balancing schemeIEEE Transactions on Circuits and Systems I: Regular Papers, 2005
- Design Procedure for Two-Stage CMOS Transconductance Operational Amplifiers: A TutorialAnalog Integrated Circuits and Signal Processing, 2001
- A compensation strategy for two-stage CMOS opamps based on current bufferIEEE Transactions on Circuits and Systems I: Regular Papers, 1997
- An improved frequency compensation technique for CMOS operational amplifiersIEEE Journal of Solid-State Circuits, 1983