Buffer block planning for interconnect-driven floorplanning
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 16 references indexed in Scilit:
- Buffer block planning for interconnect-driven floorplanningPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An interconnect-centric design flow for nanometer technologiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Rectangle-packing-based module placementPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Interconnect delay estimation models for synthesis and design planningPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1999
- Global wires: harmful?Published by Association for Computing Machinery (ACM) ,1998
- Closed form solution to simultaneous buffer insertion/sizing and wire sizingPublished by Association for Computing Machinery (ACM) ,1997
- Delay bounded buffered tree construction for timing driven floorplanningPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- Interconnect design for deep submicron ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- Hierarchical placement and floorplanning in BEARIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Graphs in floor-plan designInternational Journal of Circuit Theory and Applications, 1988