A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer
- 1 March 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 30 (3) , 251-257
- https://doi.org/10.1109/4.364439
Abstract
A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply.<>Keywords
This publication has 13 references indexed in Scilit:
- A 1.5-ns 32-b CMOS ALU in double pass-transistor logicIEEE Journal of Solid-State Circuits, 1993
- 0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register fileIEEE Journal of Solid-State Circuits, 1992
- 2.5-V bipolar/CMOS circuits for 0.25- mu m BiCMOS technologyIEEE Journal of Solid-State Circuits, 1992
- 3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modulesIEEE Journal of Solid-State Circuits, 1992
- A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logicIEEE Journal of Solid-State Circuits, 1990
- Realization of transmission-gate conditional-sum (TGCS) adders with low latency timeIEEE Journal of Solid-State Circuits, 1989
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964
- Carry-Select AdderIRE Transactions on Electronic Computers, 1962
- An Evaluation of Several Two-Summand Binary AddersIRE Transactions on Electronic Computers, 1960
- A SIGNED BINARY MULTIPLICATION TECHNIQUEThe Quarterly Journal of Mechanics and Applied Mathematics, 1951