A model to hardware comparison of simultaneous switching noise on a CMOS chip

17 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 43-45
https://doi.org/10.1109/epep.1994.594066

Abstract

The simultaneous switching noise simulation and the comparison of those simulations to laboratory measurements of noise on a specially designed CMOS test chip on a multilayer ceramic SCM are presented.

Keywords

SEMICONDUCTOR DEVICE MODELING
HARDWARE
SEMICONDUCTOR DEVICE MEASUREMENT
NOISE MEASUREMENT
CIRCUIT NOISE
POWER SUPPLIES
PACKAGING
POWER DISTRIBUTION
CIRCUIT SIMULATION
LABORATORIES

This publication has 2 references indexed in Scilit:

Power distribution modelling of high performance first level computer packages
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Simultaneous switching noise measurement on a CMOS chip on an MLC SCM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002