Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes
- 18 January 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 08865930,p. 110-117
- https://doi.org/10.1109/cicc.2005.1568621
Abstract
This paper presents an analysis of sub-2.5-V topologies and design methodologies for SiGe BiCMOS and sub-90nm CMOS building blocks to be used in the next generation of 40-100 Gb/s wireline transceivers. Examples of optimal designs for 40-80Gb/s broadband low-noise input comparators, low-voltage high-speed MOS- and BiCMOS CML logic gates, 30-100 GHz low-noise oscillators, and 40/80 GHz output drivers with wave shape control are provided.Keywords
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