Reduced implementation of D-type DET flip-flops
- 1 March 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 28 (3) , 400-402
- https://doi.org/10.1109/4.210012
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Double-edge-triggered D-flip-flops for high-speed CMOS circuitsIEEE Journal of Solid-State Circuits, 1991
- Metastability of CMOS latch/flip-flopIEEE Journal of Solid-State Circuits, 1990
- A novel CMOS implementation of double-edge-triggered flip-flopsIEEE Journal of Solid-State Circuits, 1990
- Behavior analysis of CMOS D flip-flopsIEEE Journal of Solid-State Circuits, 1989
- High-speed CMOS circuit techniqueIEEE Journal of Solid-State Circuits, 1989
- Double-Edge-Triggered Flip-FlopsIEEE Transactions on Computers, 1981