A novel CMOS implementation of double-edge-triggered flip-flops
- 1 January 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 25 (4) , 1008-1010
- https://doi.org/10.1109/4.58294
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- MOSIS - A gateway to siliconIEEE Circuits and Devices Magazine, 1988
- A safe single-phase clocking scheme for CMOS circuitsIEEE Journal of Solid-State Circuits, 1988
- Double-Edge-Triggered Flip-FlopsIEEE Transactions on Computers, 1981