A precision FET-less sample-and-hold with high charge-to-droop current ratio
- 1 December 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (6) , 864-873
- https://doi.org/10.1109/JSSC.1978.1052061
Abstract
A monolithic sample-and-hold amplifier designed without field-effect transistors is described. Various sample-and-hold configurations are compared and their merits are discussed. Unique features of the design include a diode-bridge switch and a current booster with 50 mA of drive capability to charge the hold capacitor during large signal acquisition. The output amplifier's operating conditions are changed under logic control; it functions as a fast follower in the sample mode, and as a low input current amplifier in the hold mode. Performance characteristics include: 3.5-/spl mu/s acquisition time to 0.1 percent with a 5000-pF hold capacitor, 50 pA of droop current from 0 to 70/spl deg/C, 10/SUP 9/ charge-to-droop current ratio, and 0.3 mV of zero-scale error.Keywords
This publication has 3 references indexed in Scilit:
- A precision trim technique for monolithic analog circuitsIEEE Journal of Solid-State Circuits, 1975
- A complete monolithic sample/hold amplifierIEEE Journal of Solid-State Circuits, 1974
- Super-gain transistors for IC'sIEEE Journal of Solid-State Circuits, 1969