Design and implementation of quaternary NMOS integrated circuits for pipelined image processing
- 1 February 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (1) , 20-27
- https://doi.org/10.1109/jssc.1987.1052666
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- An NMOS pipelined image processor using quaternary logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A four-state ROM using multilevel process technologyIEEE Journal of Solid-State Circuits, 1984
- A 4-valued ECL encoder and decoder circuitIEEE Journal of Solid-State Circuits, 1982
- The Prospects for Multivalued Logic: A Technology and Applications ViewIEEE Transactions on Computers, 1981
- Computer Vision Systems for Industrial Inspection and AssemblyComputer, 1980
- High Density Integrated Computing Circuitry with Multiple Valued LogicIEEE Journal of Solid-State Circuits, 1980
- Basics of cellular logic with some applications in medical image processingProceedings of the IEEE, 1979
- Multivalued Integrated Injection LogicIEEE Transactions on Computers, 1977
- The development of multiple-valued logic as related to computer scienceComputer, 1974
- Engineering aspects of multi-valued logic systemsComputer, 1974