A newly designed planar stacked capacitor cell with high dielectric constant film for 256 Mbit DRAM
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 631-634
- https://doi.org/10.1109/iedm.1993.347281
Abstract
Thin film of (Ba/sub 0.75/Sr/sub 0.25/)TiO/sub 3/ with equivalent SiO/sub 2/ thickness of 0.47 nm has been developed for capacitor dielectric film of 256 Mbit DRAM. A novel cell design named FOGOS (FOlded Global and Open Segment bit-line cell) structure is also proposed for 256 Mbit DRAM. By combining high dielectric constant film and FOGOS design, we have succeeded in making a practical and integrated cell that has sufficient cell capacitance with planar stacked capacitor, small bitline parasitic capacitance and large lithographic tolerance of alignment and DOF. 0.72 /spl mu/m/sup 2/ cell size based on 0.25 /spl mu/m process technology is realized.<>Keywords
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