Low-power digital design
Top Cited Papers
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Recently there has been a surge of interest in low-power devices and design techniques. While many papers have been published describing power-saving techniques for use in digital systems, trade-offs between the methods are rarely discussed. We address this issue by using an energy-delay metric to compare many of the proposed techniques. Using this metric also provides insight into some of the basic trade-offs in low-power design. The next section describes the energy-loss mechanisms that are present in CMOS circuits, which provides the parameters that must be changed to lower the power dissipation. With these factors in mind, the rest of the paper reviews the energy saving techniques that have been proposed. These proposals fall into one of three main strategies: trade speed for power, do not waste power, and find a lower power problem.Keywords
This publication has 7 references indexed in Scilit:
- Adiabatic Switching, Low Energy Computing, And The Physics Of Storing And Erasing InformationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Evaluation of charge recovery circuits and adiabatic switching for low power CMOS designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A low power chipset for portable multimedia applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A low-power, area-efficient digital filter for decimation and interpolationIEEE Journal of Solid-State Circuits, 1994
- Open/folded bit-line arrangement for ultra-high-density DRAM'sIEEE Journal of Solid-State Circuits, 1994
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992
- Design of ion-implanted MOSFET's with very small physical dimensionsIEEE Journal of Solid-State Circuits, 1974