A single bitline cross-point cell activation (SCPA) architecture for ultra low power SRAMs
- 1 January 1993
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A single bitline cross-point cell activation (SCPA) architecture that reduces active power consumption and reduces the chip size of high-density SRAMs (static random access memories) is presented. The architecture enables the smallest column current possible without increasing the block division of the cell array. Since the decoder area is reduced due to less block division, the memory core can be smaller than with a conventional divided word line (DWL) structure. In the SCPA, the total active current is 15.9 mA, while in the conventional architecture it is 26.1 mA. In the SCPA, the memory cell size is equal to that in the conventional architecture; however, the number of local decoders is reduced from 64 to 8. Moreover, the number of GND lines is reduced because of a much smaller column current in SCPA. As a result, the area of the memory core is reduced by 10% in a 16-Mb SRAM.<>Keywords
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