Design methodology for defect tolerant integrated circuits

Publisher Website

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/cicc.1988.20946

Abstract

No abstract available

Keywords

This publication has 4 references indexed in Scilit:

Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI
Proceedings of the IEEE, 1984
Modeling of Integrated Circuit Defect Sensitivities
IBM Journal of Research and Development, 1983
A fault-tolerant 64K dynamic random-access memory
IEEE Transactions on Electron Devices, 1979