Parity-Scan Design to Reduce the Cost of Test Application
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 283
- https://doi.org/10.1109/test.1992.527835
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- Selectable Length Partial Scan: A Method to Reduce Vector LengthPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Ordering storage elements in a single scan chainPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Designing circuits with partial scanIEEE Design & Test of Computers, 1988
- Logic Testing and Design for TestabilityPublished by MIT Press ,1985
- On the Acceleration of Test Generation AlgorithmsIEEE Transactions on Computers, 1983