Strained Si/strained Ge dual-channel heterostructures on relaxed Si0.5Ge0.5 for symmetric mobility p-type and n-type metal-oxide-semiconductor field-effect transistors

By growing heterostructures that combine a surface strained Si layer with a buried strained Ge layer on ${\mathrm{Si}}_{\text{0.5}}{\mathrm{Ge}}_{\text{0.5}},$ we have fabricated metal-oxide-semiconductor field-effect transistors with mobility enhancement factors over bulk Si of 1.7–1.9 for electrons and 10–12 for holes. While high hole mobility can be attained in strained Si/strained Ge heterostructures grown on ${\mathrm{Si}}_{\text{0.3}}{\mathrm{Ge}}_{\text{0.7}},$ we have found the electron mobility in similarly grown heterostructures to be limited by defect scattering in the Si cap. Reducing the Ge content of the virtual substrate to ${\mathrm{Si}}_{\text{0.5}}{\mathrm{Ge}}_{\text{0.5}}$ and optimizing the strained Si and strained Ge layer thicknesses allowed the realization of devices where the $p$ -channel mobility as a function of inversion density actually matches or exceeds the $n$ -channel mobility.