Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates

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Abstract
Surface channel strained Si metal–oxide–semiconductor field-effect transistors (MOSFETs) are a leading contender for future high performance complementary metal–oxide–semiconductor (CMOS) applications. The carrier mobility enhancement of these devices is studied as a function of channel strain, and the saturation behavior for n- and p-channel devices is compared. Carrier mobility enhancements of up to 1.8 and 1.6 are achieved for n- and p-channel devices, respectively. The process stability of strained Si MOSFETs is also studied, and carrier mobility enhancement is shown to be robust after well implantation and virtual substrate planarization steps. The effects of high-temperature implant activation anneals are also studied. While no misfit dislocation introduction or strain relaxation is observed in these devices, increased interface state densities or alloy scattering due to Ge interdiffusion are shown to decrease mobility enhancements. Channel thickness effects are also examined for strained Si n-MOSFETs. Loss of carrier confinement severely limits the mobility of devices with the thinnest channels. Overall, surface channel strained Si MOSFETs are found to exhibit large carrier mobility enhancements over coprocessed bulk Si devices. This, combined with the high process stability exhibited by these devices, makes them superb candidates for future CMOS applications.