Physically realistic fault models for analog CMOS neural networks
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (9) , 1223-1229
- https://doi.org/10.1109/4.84938
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Analog electronic neural network circuitsIEEE Circuits and Devices Magazine, 1989
- VLSI implementation of a neural network modelComputer, 1988
- Electronic hardware implementations of neural networksApplied Optics, 1987
- Yield Simulation for Integrated CircuitsPublished by Springer Nature ,1987
- VLASIC: A Catastrophic Fault Yield Simulator for Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Modeling the critical area in yield forecastsIEEE Journal of Solid-State Circuits, 1985
- Modeling of Lithography Related Yield Losses for CAD of VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Inductive Fault Analysis of MOS Integrated CircuitsIEEE Design & Test of Computers, 1985
- Modeling of defects in integrated circuit photolithographic patternsIBM Journal of Research and Development, 1984
- Neural networks and physical systems with emergent collective computational abilities.Proceedings of the National Academy of Sciences, 1982