Inductive Fault Analysis of MOS Integrated Circuits
- 1 January 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 2 (6) , 13-26
- https://doi.org/10.1109/mdt.1985.294793
Abstract
Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types and ranking of faults based on their likelihood of occurrence Hence, given the layout of an IC, a fault model and a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics. The IFA procedure is illustrated by its applications to an example circuit. The results from this sample led to some very interesting observations regarding nonclassical faults.Keywords
This publication has 8 references indexed in Scilit:
- VLASIC: A Catastrophic Fault Yield Simulator for Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Modeling of Lithography Related Yield Losses for CAD of VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- The Design of Easily Testable VLSI Array MultipliersIEEE Transactions on Computers, 1984
- Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSIProceedings of the IEEE, 1984
- Modeling of Integrated Circuit Defect SensitivitiesIBM Journal of Research and Development, 1983
- Fault Diagnosis of MOS Combinational NetworksIEEE Transactions on Computers, 1982
- Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their TestabilityIEEE Transactions on Computers, 1980
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978