Fault Diagnosis of MOS Combinational Networks
- 1 February 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-31 (2) , 129-139
- https://doi.org/10.1109/tc.1982.1675958
Abstract
The increasing difficulties in testing large logic networks have generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks with and without fan-in, fan-out constraints were described in previous papers by the authors. In this two-part series, we discuss the testing of these designed networks.Keywords
This publication has 15 references indexed in Scilit:
- Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical ResultsIEEE Transactions on Computers, 1978
- Logic Design Automation of MOS Combinational Networks with Fan-In, Fan-Out ConstraintsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978
- On the Design of Logic Networks with Redundancy and Testability ConsiderationsIEEE Transactions on Computers, 1974
- Complete Test Sets for Logic FunctionsIEEE Transactions on Computers, 1973
- Fault Detection in Fanout-Free Combinational NetworksIEEE Transactions on Computers, 1973
- Derivation of Minimal Test Sets for Monotonic Logic CircuitsIEEE Transactions on Computers, 1973
- A Design Procedure for Fault-Locatable Switching CircuitsIEEE Transactions on Computers, 1972
- Easily Testable Realizations ror Logic FunctionsIEEE Transactions on Computers, 1972
- Detection of Multiple Faults in Combinational Logic NetworksIEEE Transactions on Computers, 1972
- Derivation of Minimum Test Sets for Unate Logical CircuitsIEEE Transactions on Computers, 1971