Complete Test Sets for Logic Functions
- 1 November 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-22 (11) , 1016-1020
- https://doi.org/10.1109/t-c.1973.223638
Abstract
The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks. It is further indicated that even in the presence of redundancies in the network, the test sets given remain valid.Keywords
This publication has 7 references indexed in Scilit:
- A Design Procedure for Fault-Locatable Switching CircuitsIEEE Transactions on Computers, 1972
- Easily Testable Realizations ror Logic FunctionsIEEE Transactions on Computers, 1972
- Universal test sets for logic networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1972
- Derivation of Minimum Test Sets for Unate Logical CircuitsIEEE Transactions on Computers, 1971
- Cause-Effect Analysis for Multiple Fault Detection in Combinational NetworksIEEE Transactions on Computers, 1971
- Unate Cellular LogicIEEE Transactions on Computers, 1969
- Fault Detection in Redundant CircuitsIEEE Transactions on Electronic Computers, 1967