Managing Wire Delay in Large Chip-Multiprocessor Caches

This publication has 36 references indexed in Scilit:

• A case for shared instruction cache on chip multiprocessors running OLTP
  ACM SIGARCH Computer Architecture News, 2003
• Simulating a $2M commercial server on a $2K PC
  Computer, 2003
• Implementation of a third-generation 1.1-GHz 64-bit microprocessor
  IEEE Journal of Solid-State Circuits, 2002
• The Stanford Hydra CMP
  IEEE Micro, 2000
• The MAJC architecture: a synthesis of parallelism and scalability
  IEEE Micro, 2000
• UltraSPARC-III: designing third-generation 64-bit performance
  IEEE Micro, 1999
• Effective hardware-based data prefetching for high-performance processors
  IEEE Transactions on Computers, 1995
• A performance study of software and hardware data prefetching schemes
  ACM SIGARCH Computer Architecture News, 1994
• DDM-a cache-only memory architecture
  Computer, 1992
• Cache operations by MRU change
  IEEE Transactions on Computers, 1988