A new diagnosis approach for short faults in interconnects
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 331-339
- https://doi.org/10.1109/ftcs.1995.466966
Abstract
Existing one-step diagnosis approaches for faults in interconnects either yield a long test sequence, or use a non-generalized procedure to generate a shorter test sequence. We propose a new diagnosis approach for short faults in interconnects. The pin-adjacency fault model is assumed. By using a divide-and-conquer strategy, our approach can generate a very compact test vector sequence which can diagnose an unrestricted number of short faults. Our experiments for three benchmarks as well as large random interconnects (up to 50,000 nets) show that our approach can achieve more than 50% savings in the length of the generated test sequence. This can significantly save the diagnosis cost for boundary-scan testing. An adaptive diagnosis approach is further proposed to dynamically truncate the originally generated test sequence based on the current information of faulty nets. The performance of our adaptive approach in terms of the on-line test generation time and the resulting test sequence length is better than for existing adaptive diagnosis approaches when the fault rate is not very small, such as in a new product line. If a low complexity for the ATE is of major importance, then the proposed one-step approach is the best choice.<>Keywords
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