A New Economical Implementation for Scannable Flip-Flops in MOS
- 1 June 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 3 (3) , 52-56
- https://doi.org/10.1109/mdt.1986.294994
Abstract
A New implementation for scannable flip-flops in MOS is economical for use in systems that use single latch design. The "System Latch-Scannable Flop" (SL-SF) requires two additional transfer gates, two test clocks, and possibly a test mode signal. Hardware pernalties paid in SL-SF can be the least among other implementations with equivalent test functionality. This article discusses SL-SF only in the context of its scan-path implementation; its applicability to linear feedback shift-register-based self-test should be obvious.Keywords
This publication has 3 references indexed in Scilit:
- Built-In Self-Test StructuresIEEE Design & Test of Computers, 1985
- A novel clocking technique for VLSI circuit testabilityIEEE Journal of Solid-State Circuits, 1984
- Design for testability—A surveyProceedings of the IEEE, 1983