10 Gbit/s bit-synchronizer with automatic retiming clock alignment using quantum well AlGaAs/GaAs/AlGaAs technology
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 217-220
- https://doi.org/10.1109/gaas.1991.172676
Abstract
A 10 Gb/s bit-synchronizer circuit has been fabricated using an enhancement/depletion 0.3 mu m recessed-gate AlGaAs/GaAs/AlGaAs quantum well FET process. The differential gain of the phase comparator circuit is measured to be 371 mV/rad. The phase margins for monotonous phase comparison are -54/+21 degree relative to the in bit cell center position of the clock edge. The chip has a power dissipation of 160 mW at a supply of 1.90 V.Keywords
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