An advanced 0.5- mu m CMOS disposable TiN LDD/salicide spacer process
- 1 July 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 11 (7) , 318-320
- https://doi.org/10.1109/55.56487
Abstract
An advanced 0.5- mu m CMOS technology which features disposable TiN spacers to define both lightly doped drain (LDD) implantation and self-aligned silicided source, drain, and gate regions is discussed. Since the LDD implantation sequences are reversed using the disposable TiN spacers, this process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus N/sup -/ and boron P/sup -/ regions for improved short-channel behavior.Keywords
This publication has 4 references indexed in Scilit:
- An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The effect of implantation damage on arsenic/phosphorus codiffusionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Experimental derivation of the source and drain resistance of MOS transistorsIEEE Transactions on Electron Devices, 1980
- Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistorIEEE Transactions on Electron Devices, 1980