Nibble-serial arithmetic processor designs via unfolding
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 635-640 vol.1
- https://doi.org/10.1109/iscas.1989.100432
Abstract
The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two's-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W/sub 1/-b of a word or sample in a single cycle, and the complete word is input in W/sub 2/ cycles, where W=W/sub 1/W/sub 2/ is the word length. W/sub 1/ need not be 4 in a nibble-serial implementation, but can be any divisor of the word length.Keywords
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