A 1-V high-speed MTCMOS circuit scheme for power-down application circuits
- 1 June 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (6) , 861-869
- https://doi.org/10.1109/4.585288
Abstract
No abstract availableThis publication has 8 references indexed in Scilit:
- A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 1-V high-speed MTCMOS circuit scheme for power-down applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 50% active-power saving without speed degradation using standby power reduction (SPR) circuitPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOSIEEE Journal of Solid-State Circuits, 1995
- Subthreshold-current reduction circuits for multi-gigabit DRAM'sIEEE Journal of Solid-State Circuits, 1994
- Open/folded bit-line arrangement for ultra-high-density DRAM'sIEEE Journal of Solid-State Circuits, 1994
- A low-power chipset for a portable multimedia I/O terminalIEEE Journal of Solid-State Circuits, 1994
- Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI'sIEEE Journal of Solid-State Circuits, 1993