Subthreshold-current reduction circuits for multi-gigabit DRAM's
- 1 July 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 29 (7) , 761-769
- https://doi.org/10.1109/4.303713
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Power-supply considerations for future scaled CMOS systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Subthreshold-current reduction circuits for multi-gigabit DRAM'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Stand-by/active mode logic for sub-1 V 1 G/4 Gb DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- New CMOS shallow junction well FET structure (CMOS-SJET) for low power-supply voltagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- A 4-Mb low-temperature DRAMIEEE Journal of Solid-State Circuits, 1991
- A 23-ns 1-Mb BiCMOS DRAMIEEE Journal of Solid-State Circuits, 1990
- A 1.5-V DRAM for battery-based applicationsIEEE Journal of Solid-State Circuits, 1989
- Generalized scaling theory and its application to a ¼ micrometer MOSFET designIEEE Transactions on Electron Devices, 1984
- Design of ion-implanted MOSFET's with very small physical dimensionsIEEE Journal of Solid-State Circuits, 1974