A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensation
- 7 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Low-jitter and process independent DLL and PLL based on self biased techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A semi-digital DLL with unlimited phase shift capability and 0.08-400 MHz operating rangePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 700-Mb/s/pin CMOS signaling interface using current integrating receiversIEEE Journal of Solid-State Circuits, 1997