Figaro - an automatic tool flowfor designs with dynamic reconfiguration
- 12 October 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 590-593
- https://doi.org/10.1109/fpl.2005.1515792
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA seriesPublished by Association for Computing Machinery (ACM) ,2002
- Dynamic hardware plugins in an FPGA with partial run-time reconfigurationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Improving functional density using run-time circuit reconfiguration [FPGAs]IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1998