A performance optimization method by gate sizing using statistical static timing analysis
- 1 May 2000
- proceedings article
- Published by Association for Computing Machinery (ACM)
- p. 111-116
- https://doi.org/10.1145/332357.332385
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Predicting circuit performance using circuit-level statistical timing analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Gate sizing using a statistical delay modelPublished by Association for Computing Machinery (ACM) ,2000
- Gate sizing for constrained delay/power/area optimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1997
- An exact algorithm for low power library-specific gate re-sizingPublished by Association for Computing Machinery (ACM) ,1996
- Statistical timing analysis of combinational logic circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
- Timing Analysis of Computer HardwareIBM Journal of Research and Development, 1982