Predicting circuit performance using circuit-level statistical timing analysis

This publication has 14 references indexed in Scilit:

• Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• On path selection in combinational logic circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Certified timing verification and the transition delay of a logic circuit
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Statistical timing analysis of combinational circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Path sensitization in critical path problem
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• ETA: electrical-level timing analysis
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1992
• Incremental techniques for the identification of statically sensitizable critical paths
  Published by Association for Computing Machinery (ACM) ,1991
• Asymptotic waveform evaluation for timing analysis
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
• A New Approach to Hierarchical and Statistical Timing Simulations
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
• Statistical Techniques of Timing Verification
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1983