Statistical timing analysis of combinational logic circuits
- 1 June 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 1 (2) , 126-137
- https://doi.org/10.1109/92.238423
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
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