Is redundancy necessary to reduce delay?
- 1 April 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 10 (4) , 427-435
- https://doi.org/10.1109/43.75626
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- On properties of algebraic transformation and the multifault testability of multilevel logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Static timing analysis of dynamically sensitizable pathsPublished by Association for Computing Machinery (ACM) ,1989
- Efficient algorithms for computing the longest viable path in a combinational networkPublished by Association for Computing Machinery (ACM) ,1989
- On the general false path problem in timing analysisPublished by Association for Computing Machinery (ACM) ,1989
- Timing analysis using functional analysisIEEE Transactions on Computers, 1988
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A Switch-Level Timing Verifier for Digital MOS VLSIIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Redundancy and Don't Cares in Logic SynthesisIEEE Transactions on Computers, 1983
- TV: An nMOS Timing AnalyzerPublished by Springer Nature ,1983
- Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic UnitsIEEE Transactions on Electronic Computers, 1961