A design for testability technique for RTL circuits using control/data flow extraction
- 23 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- Sequential circuit design using synthesis and optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Partial scan at the register-transfer levelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheadsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- HITEC: a test generation package for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An iterative improvement algorithm for low power data path synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- High-level synthesis for testabilityPublished by Association for Computing Machinery (ACM) ,1996
- A transitive closure algorithm for test generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Fast prototyping of datapath-intensive architecturesIEEE Design & Test of Computers, 1991
- Hierarchical test generation using precomputed tests for modulesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990