Small-size low-power bipolar memory cell
- 1 October 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 6 (5) , 283-288
- https://doi.org/10.1109/jssc.1971.1050188
Abstract
A d.c.-stable random-access memory (RAM) cell employing n-p-n and p-n-p transistors has been designed in a concurrent circuit-layout approach. Test chips with 2×3 arrays have been processed in a standard bipolar technology. Due to the merging of devices, the area required for a cell is only 14 mil2. The cells have been operated at an extremely low d.c. standby power of less than 0.1 μW/cell. In spite of this low standby power, an array access time of 10 ns has been measured on a simulated 512-bit array in a pulsed power mode.Keywords
This publication has 5 references indexed in Scilit:
- Two-terminal transistor memory cell using breakdownPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1971
- Small-size, low-power bipolar memory cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1971
- 100-ns electronically variable semiconductor memory using two diodes per memory cellIEEE Journal of Solid-State Circuits, 1970
- Low-power bipolar transistor memory cellsIEEE Journal of Solid-State Circuits, 1969
- Silicon-gate technologyIEEE Spectrum, 1969