A comparison of gettering techniques for very large scale integration

Abstract
Two techniques developed for metal‐oxide‐semiconductor (MOS) processing, internal gettering (IG) and silicon gettering by segregation, are compared. The test vehicles are n+/p junction diodes and are tested for their reverse current and defect density. The forward characteristic of these diodes is ideal over about six orders of magnitude with slope 60 mV/decade. No generation‐recombination current affects the characteristic. Some diodes, though with an ideal forward characteristic, behave for reverse bias as I=I0+V/R, where I0 is the current extrapolated at V=0 and R is an apparent resistance. Taking into account that the width of the depletion layer is of the order of 1–3 μm, the ‘‘resistivity’’ responsible for the ‘‘resistance’’ R is of the order of 1011–1014 Ω cm, depending on the particular diode. The parameters I0 and R are correlated over about four orders of magnitude by the relationship 1/RI0Idiff, where Idiff is the diffusion current determined by the forward characteristic. The ‘‘resistance’’ R depends to a slight extent on the thermal history of the diode, but mainly on the final anneal temperature. Ideal diodes are particular diodes with I0=Idiff.