Layer assignment for VLSI interconnect delay minimization
- 1 June 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 8 (6) , 702-707
- https://doi.org/10.1109/43.31525
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- Efficient Algorithms for Layer Assignment ProblemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- An Unconstrained Topological Via Minimization Problem for Two-Layer RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- Signal Delay in RC Tree NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- A graph-theoretic via minimization algorithm for two-layer printed circuit boardsIEEE Transactions on Circuits and Systems, 1983
- A Linear-Time Heuristic for Improving Network PartitionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- An Optimum Layer Assignment for Routing in ICs and PCBsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- Wire routing by optimizing channel assignment within large aperturesPublished by Association for Computing Machinery (ACM) ,1971
- An Efficient Heuristic Procedure for Partitioning GraphsBell System Technical Journal, 1970
- The Transient Response of Damped Linear Networks with Particular Regard to Wideband AmplifiersJournal of Applied Physics, 1948