Layout-dependent fault analysis and test synthesis for CMOS circuits

This publication has 30 references indexed in Scilit:

• THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Modeling of gate oxide shorts in MOS transistors
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
• Physical failures and fault models of CMOS circuits
  IEEE Transactions on Circuits and Systems, 1987
• Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
  IEEE Transactions on Computers, 1986
• On the Acceleration of Test Generation Algorithms
  IEEE Transactions on Computers, 1983
• CAzM: A circuit analyzer with macromodeling
  IEEE Transactions on Electron Devices, 1983
• An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
  IEEE Transactions on Computers, 1981
• Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
  IEEE Transactions on Computers, 1980
• Controllability/observability analysis of digital circuits
  IEEE Transactions on Circuits and Systems, 1979
• Diagnosis of Automata Failures: A Calculus and a Method
  IBM Journal of Research and Development, 1966