Multiplier design utilizing improved column compression tree and optimized final adder in CMOS technology
- 31 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 209-212
- https://doi.org/10.1109/vtsa.1993.263604
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
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- Circuit and architecture trade-offs for high-speed multiplicationIEEE Journal of Solid-State Circuits, 1991
- SPIM: a pipelined 64*64-bit iterative multiplierIEEE Journal of Solid-State Circuits, 1989